Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
10.6.2004
P0, P1,
P2, P3
Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
6 Chnl
PCA
128 kB
FLASH
256 Byte
RAM
VDD
Monitor
SFR Bus
8
0
5
1
C
o
r
e
Timers
0, 1, 2, 4
Timer 3
P0
Drv
C
R
O
S
S
B
A
R
AV+
AV+
VDD
VDD
VDD
DGND
DGND
DGND
AGND
AGND
Reset
RST
XTAL1
XTAL2
External
Oscillator
Circuit
System
Clock
Internal
2%
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
8 kB
XRAM
P2.0
P2.7
P1.0/AIN1.0
P1.7/AIN1.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus Control
DAC1
DAC1
(12-Bit)
VREF
DAC0
(12-Bit)
ADC
100 ksps
(10-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DAC0
CP0+
CP0-
CP1+
CP1-
VREF
TEMP
SENSOR
UART0
P3.0
P3.7
P3
Drv
Prog
Gain
ADC
500 ksps
(8-Bit)
A
M
U
X
8:1
MONEN
WDT
VREF1
VREFD
VREF0
CP0
CP1
C
T
L
P4 Latch
D
a
t
a
P7 Latch
A
d
d
r
P5 Latch
P6 Latch
P7.0/D0
P7.7/D7
P7
DRV
P5.0/A8
P5.7/A15
P5
DRV
P6.0/A0
P6.7/A7
P6
DRV
P4
DRV
P4.5/ALE
P4.6/RD
P4.7/WR
P4.0
P4.4
External Data Memory Bus
256 Byte
Branch
Target Buffer
N/M
PLL
Prefetch
HW
32
8
Prog
Gain
C8051F126
50 MIPS, 128 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
-
1 LSB INL; no missing codes
-
Programmable throughput up to 100 ksps
-
8 external inputs; programmable as single-ended or differential
-
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-
Data-dependent windowed interrupt generator
-
Built-in temperature sensor (3 C)
8-Bit ADC
-
1 LSB INL; no missing codes
-
Programmable throughput up to 500 ksps
-
8 external inputs
-
Programmable amplifier gain: 4, 2, 1, 0.5
Two 12-Bit DACs
-
Can synchronize outputs to timers for jitter-free waveform generation
Two Comparators
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
-
Provides breakpoints, single stepping, watchpoints, stack monitor
-
Inspect/modify memory and registers
-
Real-time instruction trace buffer
-
IEEE1149.1 compliant boundary scan
High-Speed 8051 C Core
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
Up to 50 MIPS Throughput with 50 MHz system clock
-
Expanded interrupt handler
Memory
-
8448 bytes data RAM
-
128 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes
are reserved)
-
External parallel data memory interface
Digital Peripherals
-
64 port I/O; all are 5 V tolerant
-
Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial
ports available concurrently
-
Programmable 16-bit counter/timer array with six capture/compare
modules
-
5 general-purpose 16-bit counter/timers
-
Dedicated watchdog timer; bidirectional reset
-
Real-time clock mode using a timer or PCA
Clock Sources
-
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
-
On-chip programmable PLL: up to 50 MHz
-
External oscillator: Crystal, RC, C, or Clock
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 25 mA at 50 MHz
-
Typical stop mode current: <0.1 uA
100-Pin TQFP
Temperature Range: 40 to +85 C
Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
10.6.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F126
50 MIPS, 128 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU
Selected Electrical Specifications
(T
A
= 40 to +85 C, V
DD
= 2.7 V unless otherwise specified)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Supply
Voltage
2.7 3.6
V
Supply Current
(CPU active)
Clock = 50 MHz
Clock = 1 MHz
Clock = 32 kHz
25
0.5
16
mA
mA
A
Supply Current
(shutdown)
Oscillator off; V
DD
Monitor Enabled
Oscillator off; V
DD
Monitor Disabled
10
<0.1
A
A
Clock Frequency Range
DC
50
MHz
INTERNAL CLOCKS
Oscillator Frequency
24.0
24.5
25.0
MHz
PLL Frequency
48
49
50
MHz
A/D CONVERTER
Resolution
10 bits
Integral Nonlinearity
1
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
LSB
Signal-to-Noise Plus
Distortion
59
61
dB
Throughput Rate
100
ksps
D/A CONVERTERS
Resolution
12 bits
Differential Nonlinearity
Guaranteed Monotonic
1
LSB
Output Settling Time
10
S
COMPARATORS
Supply Current
(each Comparator)
1.5
A
Response Time
(CP+) (CP-) = 100 mV
4.0
S
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
0.95
0.17
-
-
-
-
-
-
-
1.00
0.22
16.00
14.00
0.50
16.00
14.00
1.20
0.15
1.05
0.27
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
100
e
A1
b
A2
A
PIN 1
DESIGNATOR
1
E1
E
D1
D
C8051F120DK Development Kit
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